What is a Page Table Entry?
Virtual memory relies on a contract between hardware (the Memory Management Unit, or MMU) and the operating system kernel. When a process issues a virtual memory address, the hardware extracts the high-order bits representing the Virtual Page Number (VPN) and uses them as an array index into the process's page table.
Each slot in that array is a single Page Table Entry (PTE). In modern 64-bit systems, each PTE is typically an 8-byte (64-bit) data structure. Its job is twofold:
- Provide Physical Translation: Map the virtual page to its current physical frame in DRAM via the Page Frame Number (PFN).
- Store Hardware Control Flags: Convey permissions, memory residency, and access history via status bits inspected directly by hardware on every instruction fetch, read, or write.
Because physical DRAM is partitioned into fixed 4 KB (212-byte) boundaries, the low 12 bits of any address are identical in both virtual and physical memory. This leaves the lowest bits of the PTE free to store critical control flags rather than redundant address bits.
Part 2: Interactive Sandbox & MMU Tester
Click on any flag bit in the PTE below to toggle it manually, then issue read/write requests to watch the MMU react in real time.
| Bit | Full Name | Role in Hardware MMU |
|---|---|---|
| Present | Present / Absent | 1 = Frame in DRAM. 0 = On disk; access triggers a Page Fault. |
| Protection | Protection | 0 = Read-only. 1 = Read & Write allowed. |
| Referenced | Referenced | Hardware sets to 1 on read/write. Cleared by OS clock ticks. |
| Modified | Modified (Dirty) | Hardware sets to 1 on write. If 1, page must be saved to disk on eviction. |
| Caching | Caching Disabled | 1 = Bypasses CPU L1/L2 caches; used for memory-mapped I/O registers. |
| Supervisor | User / Supervisor | 0 = Userland accessible. 1 = Kernel/Supervisor mode only. |