1. The Hardware-to-Kernel Page Fault Pipeline
When a CPU instruction references a virtual memory address whose page table entry (PTE) has its Present bit set to 0, the Memory Management Unit (MMU) halts execution and triggers a hardware page fault trap. Here is the complete 7-stage pipeline executed by hardware and the OS kernel:
MMU detects Present = 0 during address translation and stops instruction execution.
Hardware saves the faulting virtual address into control register CR2 and pushes an error code onto the kernel stack.
CPU switches to ring 0 and jumps to Interrupt Service Routine (Vector 14: Page Fault).
Kernel checks process Virtual Memory Areas (VMAs). If invalid, triggers a SIGSEGV (Segmentation Fault).
Kernel checks if the page is on the Inactive Standby List (Soft Fault) or requires disk I/O (Hard Fault).
Kernel assigns a physical frame, loads data if needed, updates the PTE, and sets Present = 1.
Kernel returns via iret, and the CPU re-executes the exact same instruction seamlessly.
2. What is the Inactive Standby List? (Soft Faults)
When memory pressure rises or a page is deemed infrequently accessed ("cold"), the operating system reclaims the physical frame from the process's active working set. However, reclaiming a frame does not instantly wipe its data or write it back to disk.
The OS places the reclaimed frame onto the inactive standby list. The data remains completely intact in physical RAM, but the page table entry is marked not present.
- Soft Page Fault: If the process references that page again while it is still on the standby list, the kernel performs a soft reclamation—instantly remapping the frame back to the process in microseconds without touching the slow disk swap partition!
- Recycling: If another process needs free RAM, the oldest frame on the standby list is finally overwritten or flushed to disk.
3. Classifying Translation Failures & Cost Spectrum
Whenever the CPU fetches an instruction or reads/writes memory, the hardware MMU attempts translation. If the mapping is not immediately resolvable, execution is interrupted by a hardware trap. The cost of resolving this trap spans five orders of magnitude depending on where the pipeline halts:
- TLB Hit (< 1 ns): Resolved purely in CPU associative registers. Zero DRAM access, zero OS code.
- Soft Miss / Minor Fault (10–50 ns): The physical frame is already in DRAM (e.g. shared libraries, clean standby page, or copy-on-write clone). The kernel handles the trap entirely in software by inserting the translation into the PTE and TLB. Zero disk I/O.
- Hard Miss / Major Fault (1–10 ms): The page is completely absent from physical RAM. The thread is put to sleep while an asynchronous DMA storage read fetches the page from SSD swap or an ELF binary on disk.
- Segmentation Violation / SIGSEGV: The address does not fall within any allocated Virtual Memory Area (VMA) belonging to the process. The kernel sends
SIGSEGVto terminate the offending thread.
Part 2: Interactive Fault Dispatcher
Dispatch instructions against real virtual memory segments to watch the hardware gates and OS handlers trigger step-by-step.
| VMA Region | Virt Page | Hardware Status | Physical Location |
|---|---|---|---|
| User Stack | 0x7FF0 | Mapped in TLB | DRAM Frame 42 |
| Shared Library | 0x5000 | Uncached in TLB | DRAM Page Cache |
| Inactive Standby | 0x3200 | Unmapped in PTE | DRAM Free List |
| Anonymous Heap | 0x2000 | P = 0 (Absent) | Swap Partition (SSD) |
| ELF Text Segment | 0x0400 | P = 0 (Demand-paged) | Binary Executable (Disk) |
| Unmapped Space | 0x0000 | NULL Pointer | None (Invalid VMA) |