Two-Level Page Table Translation

Tanenbaum Fig 3-13: Deconstructing a 32-bit virtual address into Top-Level (PT1), Second-Level (PT2), and Offset fields.

Guided Walkthrough Step 1 of 4
32-Bit Virtual Address Breakdown
PT1 (Bits 31-22) 0000000001 (1)
PT2 (Bits 21-12) 0000000011 (3)
Offset (Bits 11-0) 000000000100 (4)
Top-Level Directory Index [0..1023]
PT2 Table (for PT1=1) Index [0..1023]
Hardware MMU Physical Bus
Virtual Addr: 0x00403004
Decoded: PT1=1, PT2=3, Offset=4
Page Frame Number (PFN): PFN 65
Physical Frame Base: 0x00041000
Physical Address (+Offset): 0x00041004

Notice how top-level entries without active mappings hold NULL, meaning the entire 4 MB second-level table does not need to exist in memory.